technical data IN74AC163 presettable counters high-speed silicon-gate cmos ordering information IN74AC163n plastic IN74AC163d soic t a = -40 to 85 c for all packages the IN74AC163 is identical in pinout to the ls/als163, hc/hct163. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with ls/als outputs. the IN74AC163 is programmable 4-bit synchronous modulo-16 counter that feature parallel load, synchronous reset, a carry output for cascading and count-enable controls. the IN74AC163 is binary counter with synchronous reset. ? outputs directly interf ace to cmos, nmos, and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1.0 a; 0.1 a @ 25 c ? high noise immunity characteristic of cmos devices ? outputs source/sink 24 ma logic diagram pin 16 =v cc pin 8 = gnd function table inputs outputs reset load rev. 00 enable p enable t clock q0 q1 q2 q3 function l x x x l l l l reset to ?0? h l x x p0 p1 p2 p3 preset data h h x l no change no count h h l x no change no count h h h h count up count x x x x no change no count pin assignment x=don?t care p0,p1,p2,p3 = logic level of data inputs ripple carry out = enable t ? q0 ? q1 ? q2 ? q3
IN74AC163 rev. 00 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) -0.5 to +7.0 v v in dc input voltage (referenced to gnd) -0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc supply current, v cc and gnd pins 50 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw tstg storage temperature -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the reco mmended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t j junction temperature (pdip) 140 c t a operating temperature, all package types -40 +85 c i oh output current - high -24 ma i ol output current - low 24 ma t r , t f input rise and fall time * (except schmitt inputs) v cc =3.0 v v cc =4.5 v v cc =5.5 v 0 0 0 150 40 25 ns/v * v in from 30% to 70% v cc this device contains protection circuitry to guard agains t damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage highe r than maximum rated voltages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
IN74AC163 rev. 00 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limits symbol parameter test conditions v 25 c -40 c to 85 c unit v ih minimum high- level input voltage v out =0.1 v or v cc -0.1 v 3.0 4.5 5.5 2.1 3.15 3.85 2.1 3.15 3.85 v v il maximum low - level input voltage v out = v cc -0.1 v 3.0 4.5 5.5 0.9 1.35 1.65 0.9 1.35 1.65 v v oh minimum high- level output voltage i out -50 a 3.0 4.5 5.5 2.9 4.4 5.4 2.9 4.4 5.4 v * v in =v ih or v il i oh =-12 ma i oh =-24 ma i oh =-24 ma 3.0 4.5 5.5 2.56 3.86 4.86 2.46 3.76 4.76 v ol maximum low- level output voltage i out 50 a 3.0 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 v * v in =v ih i ol =12 ma i ol =24 ma i ol =24 ma 3.0 4.5 5.5 0.36 0.36 0.36 0.44 0.44 0.44 i in maximum input leakage current v in =v cc or gnd 5.5 0.1 1.0 a i old +minimum dynamic output current v old =1.65 v max 5.5 75 ma i ohd +minimum dynamic output current v ohd =3.85 v min 5.5 -75 ma i cc maximum quiescent supply current (per package) v in =v cc or gnd 5.5 8.0 80 a * all outputs loaded; thresholds on input associated with output under test. +maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc
IN74AC163 rev. 00 ac electrical characteristics (c l =50pf,input t r =t f =3.0 ns) v cc * guaranteed limits symbol parameter v 25 c -40 c to 85 c unit min max min max f max maximum clock frequency (figure 1) 3.3 5.0 70 110 60 95 mhz t plh propagation delay clock to q (figure 1) 3.3 5.0 2.0 1.5 12.0 9.0 1.5 1.0 13.5 9.5 ns t phl propagation delay clock to q (figure 1) 3.3 5.0 1.5 1.5 12.5 9.5 1.5 1.5 13.0 10.0 ns t plh propagation delay, clock to ripple cary out (figure 1) 3.3 5.0 3.0 2.0 15.0 10.5 2.5 1.5 16.5 11.5 ns t phl propagation delay, clock to ripple cary out (figure 1) 3.3 5.0 3.5 2.0 14.0 11.0 2.5 2.0 15.5 11.5 ns t plh propagation delay, enable t to ripple carry out (figure 2) 3.3 5.0 2.0 1.5 9.5 6.5 1.5 1.0 11.0 7.5 ns t phl propagation delay, enable t to ripple carry out (figure 2) 3.3 5.0 2.5 2.0 11.0 8.5 2.0 1.5 12.5 9.5 ns c in maximum input capacitance 5.0 4.5 4.5 pf typical @25 c,v cc =5.0 v c pd power dissipation capacitance 45 pf * voltage range 3.3 v is 3.3 v 0.3 v voltage range 5.0 v is 5.0 v 0.5 v
IN74AC163 rev. 00 timing requirements (c l =50pf,input t r =t f =3.0 ns) v cc guaranteed limit symbol parameter v +25 c -40 c to +85 c unit t su minimum setup time, preset data inputs to clock (figure 4) 3.3 5.0 13.5 8.5 16.0 10.5 ns t h minimum hold time, clock to preset data inputs (figure 4) 3.3 5.0 -1.0 0 -0.5 0 ns t su minimum setup time, reset to clock (figure 3) 3.3 5.0 14 9.5 16.5 11.0 ns t h minimum hold time, clock to reset (figure 3) 3.3 5.0 -1.0 -0.5 -0.5 0 ns t su minimum setup time, load to clock (figure 5) 3.3 5.0 11.5 7.5 14.0 8.5 ns t h minimum hold time, clock to load or preset data inputs (figure 5) 3.3 5.0 -1.0 -0.5 -0.5 0 ns t su minimum setup time, enable t or enable p to clock (figure 5) 3.3 5.0 6.0 4.5 7.0 5.0 ns t h minimum hold time, clock to enable t or enable p (figure 5) 3.3 5.0 0 0 0 0.5 ns t w minimum pulse width, (load) (figure 3) 3.3 5.0 3.5 2.5 4.0 3.0 ns t w minimum pulse width, (count) (figure 3) 3.3 5.0 4.0 3.0 4.5 3.5 ns
IN74AC163 figure 1. switching waveform figure 2. switching waveform figure 3. switching waveform figure 4. switching waveform figure 5. switching waveform rev. 00
IN74AC163 sequence illustrated in waveforms: 1. reset outputs to zero. 2. preset to binary twelve. 3. count to thirteen, fourteen, fifteen, zero, one, and two. 4. inhibit. figure 8. timing diagram rev. 00
IN74AC163 expanded logic diagram rev. 00
IN74AC163 n suffix plastic dip (ms - 001bb) symbol min max a 18.67 19.69 b 6.1 7.11 c 5.33 d 0.36 0.56 f 1.14 1.78 g h j 0 10 k 2.92 3.81 notes: l 7.62 8.26 1. dimensions ?a?, ?b? do not include mold flash or protrusions. m 0.2 0.36 maximum mold flas h or protrus ions 0.25 mm (0.010) per s ide. n 0.38 d suffix soic (ms - 012ac) symbol min max a 9.8 10 b 3.8 4 c 1.35 1.75 d 0.33 0.51 f 0.4 1.27 g h j 0 8 notes: k 0.1 0.25 1. dimensions a and b do not include mold flash or protrusion. m 0.19 0.25 2. maximum mold flas h or protrus ion 0.15 mm (0.006) per s ide p 5.8 6.2 for a; for b ? 0.25 mm (0.010) per s ide. r 0.25 0.5 5.72 2.54 7.62 1.27 dimens ion, mm dimens ion, mm a b h c k c m j f m p g d r x 45 seating plane 0.25 (0.010) m t -t- 1 16 8 9 l h m j a b f g d seating plane n k 0.25 (0.010) m t -t- c 1 16 8 9 rev. 00
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